The present invention relates to a circuit for correcting a duty ratio of a pulse supplied from a pulse generator or the like.
Assume that an LSI (Large Scale Integration) performs processing with a clock generated by an PLL (Phase-Locked Loop) circuit or the like inside the chip of the LSI. Generally in this case, the PLL circuit or the like does not guarantee the duty ratio of the clock. It is therefore necessary to provide another means for generating a pulse with a desired duty ratio, for example, a duty ratio of 50% based on the generated clock.
In order to obtain a pulse with a duty ratio of 50% using an PLL circuit in the background art, for example, there has been used a technique in which an PLL output with a frequency twice as high as a desired frequency is generated, and the PLL output is divided to obtain a pulse with a duty ratio of 50%. According to this technique, it is possible to generate a pulse with a considerably accurate duty ratio. However, there occurs a disadvantage on design that power consumption increases to generate the PLL output with a frequency twice as high as a desired one.
For this reason, for example, a technique disclosed in JP-UM-H01-70427A. This technique will be described with reference to FIG. 3. An output of an oscillator 14 is put into a comparator 16 so as to be converted into a pulse signal CK shaped into a rectangular wave. This pulse signal CK is supplied to an output terminal 18 as a clock pulse. An integration circuit 24 constituted by a resistor 20 and a capacitor 22 integrates the pulse signal CK and generates a voltage signal QV indicating an average DC level of the pulse signal.
On the other hand, a volume circuit 28 serves to set a reference voltage BV defining the duty ratio. A comparator circuit 26 compares the voltage signal QV with the reference voltage BV and outputs a deviation between the both as an error signal EV. An integration circuit 34 constituted by a resistor 30 and a capacitor 32 integrates the error signal EV so as to generate a comparison signal CV and negatively feed the comparison signal CV back to the comparative 16. In such a manner, the voltage signal QV depending on the duty ratio of the pulse signal CK is negatively fed back to the comparator 16 so as to adjust the duty ratio of the clock pulse to a desired value.
Due to recent tendency to increase the speed of a clock pulse, the capacitor 22, 32 used in each integration circuit 24, 34 cannot help but having a large capacity to some degree. Thus, there occurs a problem that there is a limit in improvement of response so that the speed cannot be increased. In addition, when the technique is applied to a circuit inside an LSI, there occurs a problem that the chip area to form each capacitor 22, 32 increases.